Chip Design and ASIC Verification Basics in 2021

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Chip Design and ASIC Verification Basics in 2021

Engineering Insights

In a world dominated by apps and software, little or no attention is given to the actual hardware that allows apps and software to run, also known as ASIC verification. The chip, as the smallest part of any computer or laptop component, is also the most important component of any hardware system. Also known as IC (Integrated Circuits) or ASIC (Application Specific Integrated Circuit), each chip is designed to implement a specific function.


Despite looking tiny, a single ASIC has the potential to hold billions of transistors. Thus, the fabrication process is extremely costly. The same goes true for the verification process, which undergoes several stages to ensure that the chip works as designed. 

ASIC verification is quite a challenging task that requires hours of testing and numerous optimizations. Even though there are no two projects alike, we can pinpoint several chip design verification steps that can be found in any successful verification project.

Verification Approaches

The verification can be split into several approaches. For instance, the top-down verification approach includes a system to individual components, while the bottom-up verification approach involves individual components of the system. You can also have a platform-based verification approach, where the developer verifies IPs in an existing platform.

Ultimately, you can also have a system interface-based verification approach, which is suitable for the final integration verification and models each block at the interface level.

Verification Technologies

There are several technologies used in the verification of ASIC. They are broken down into Functional Verification, Formal Verification, and Emulation & Acceleration:

1. Functional Verification: ensures the design works according to the original specs.

2. Formal Verification: uses formal methods of mathematical verification to ensure the design requirements are met.

3. Emulation & Acceleration:

  • In-system verification
  • Highest performance
  • Highest capacity
  • Real system environment

Tools Used for Verifications

In order to verify the chip, engineers can use various tools, ranging from pre-developed simulation models and emulation to the ASIC test chip and FPGA. With emulation, for instance, they can verify designs using real hardware or can use interfaces with real HW components. On the other hand, FPGA can enable automatic partitioning and routing.

The Verification Process

Step 1: Specifications

The specification is the first step of an ASIC design verification. This step includes a set of requirements that should be met and hold true across all possible operating requirements of the process, voltage, and temperature, as well as across all mismatches for a particular circuit.  How much detail a spec contains depends on the particular situation, but it at least covers all the necessary information needed for the design in an unambiguous manner.

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In this first step, it is also paramount for the engineers to consult with the architect in order to fully understand the functionality of this tool.

Step 2. Implement the Verification Environment

After the specs have been created and a verification plan is in place, engineers need to use an HVL, or verification environment, to check the ASIC. This process requires advanced programming skills

Step 3. Running Regressions

Next, the tests are run multiple times in order to pinpoint any potential scenario. At this point, random tests are preferred over normal tests, because they have a higher chance to find hidden weaknesses that were previously hidden.

The HVL is compiled then with the HDL or the RTL design code, and then the result is compiled and simulated. The stimulation will then produce waveforms, coverage results, and logs. These will be analyzed by the verification engineer in order to ensure that the simulation has passed.

Step 4. Sign Off

 This is the final stage of the chip design verification process. At this point, the verification engineer has to conclude if the process is actually completed. While it’s hard to ensure that all internal transitions and states were hit, or in other words, to ensure the final product works as intended, there are some mandatory things you can do to minimize the number of bugs.

  • All tests produce zero failures
  • The collected coverage is at 100%
  • No critical bugs have been found during the final testing phases

No matter your needs for chip design verification services, Tremend can help. With extensive expertise in the chip design verification market, we’re always up to date with the latest testing technologies.