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Block-Level Verification Services
Ensure the functional correctness of an ASIC and shorten the time to tape-out

The design verification process ensures that a newly developed digital or mixed-signal block functions correctly, according to the architectural specification, before it reaches the manufacturing stage. At Tremend, we strive to help our partners produce reliable designs while minimizing the time to market and costs.

Our block-level verification services

Tremend offers both Time & Material and Fixed-Price solutions to fit the needs of the organizational structure of our customers. We provide complete digital and mixed-signal design verification services, which include the following:


1. Verification activities planning
  • WBS of verification effort
  • Definition of verification effort deliverables
  • Timeline definition and management
  • Risk Register definition and management

2. Tools setup
  • Set-up of scripting infrastructure to support different tooling profiles for standalone simulation
  • Set-up of scripting infrastructure for regressions, automated build, or continuous integration
  • Additional software setup for data mining and results analysis

3. Verification metrics definition
  • Definition of Verification Plan detailing input functional space targets and stimulus generation policy
  • Definition of policies and code architecture for functional requirements traceability

4. Verification Environment development and maintenance
  • Methodology-compliant verification IP development and updates
  • Reusable and configurable environments development and updates

5. Test suite and functional coverage development
  • Coding a ready for regression tests suite with clear coverage definitions
  • Assess the test suite completeness based on functional and code coverage measurements
  • Enhance the test suite by coding directed test cases to cover the corner cases and to achieve the desired coverage

6. Regression runs
  • Implement methods for automatic testbench build
  • Provide maintenance for automated regression running
  • Implement automated reporting of regression results to engineers
  • Implement automatic nightly and weekly regression runs
  • Perform manual or automated testbench tagging

7. Debug
  • Use state of the art methods for code bugs discovery
  • Propose architectural changes to compensate for code bug fixes

8. Coverage analysis
  • Merge coverage data of multiple regression runs
  • Assist design engineers with RTL coverage analysis
  • Manage functional coverage holes by iterative review sessions with the customer and improve the grades by means of additional constraints or new test development

    Our block-level verification services cover a wide range of areas:

  • Functional verification: an essential service in ASIC development that ensures faster time to market, fewer functional defects, and improved usability or interface benefits for the final customer.
  • Formal verification: a fast turnaround method for custom IP validation that ensures quick exploration of the input space of a simple design.
  • Power-aware simulations: this procedure represents the best way to ensure that low power devices reach their electrical requirement in the field and is a sure way to help design a device with a long lifetime in day-to-day use. State-of-the-art tools are used to detect those areas where power consumption is outside the nominal range, and modern design solutions are employed to compensate.
  • Firmware verification: offering a complete System Validation process via integration of the FW code during the verification effort of an ASIC. Both digital simulation and emulation are employed. FW prototyping in close connection to the verification effort allows for fast FW development, with fewer bugs and a better API for the end-user.

Why Choose Tremend?

Tremend’s Design Verification team has a proven record of successful projects, as our clients can confirm. Our team’s focus is on high-quality deliverables and the continuous skill development of our engineers.

We ensure technological growth for each team member, from interns to highly experienced colleagues, through technical conference attendance, opportunities to learn the latest technologies, and much more.

Contact us for any type of block-level verification services needs you might have and capitalize on our promise of providing top-notch services for your specific needs.

Technologies 
Verilog
VHDL
SystemVerilog
Specman
UVM
eRM
C++
Python
Perl
TCL
Bash
TCSH

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