We provide front-end and back-end services for Digital Design, from design specifications definitions to tape-out, by mixing software and programming skills with hardware and digital circuits knowledge.
More than ever, the major tech innovators want to map out their own futures via innovative chip development, instead of trying to adapt existing infrastructure and hardware to new and unforeseen purposes. However, with great innovation comes the need for assiduous attention to detail, and a pioneering attitude rare to most tech work-spaces.
Our Chip Design and Verification Services
We have extensive knowledge in multiple areas of chip development workflow and we can provide:
1. Front-end design and verification - Tremend works with a variety of technologies and methodologies, including Cadence Xcelium Simulator, Synopsys VCS and Verdi, Mentor Questa Verification Solution, e-Language, System Verilog, UVM and eRM
- Block-Level Verification - from verification plans to block closure with full regression results analysis
- Top-Level Verification - from defining the top level verification strategy to gate level verification
- Turn-key verification IPs - delivery of tailor made verification IPs according to your project needs
- Verification Management and Methodology - help with verification management including best practices and top-notch approaches
2. Back-end - Working on various sub-micron technologies projects, Tremend’s engineers gained expertise in an optimal design and physical implementation that maximizes performance at minimum area utilization while using latest releases of tools from vendors like Synopsis, Cadence, Atoptech.
- Synthesis - Performing synthesis, analysis and debug on multi-million gate logic design using different logic/timing/power optimization techniques
- Physical Design - Expertise in the most advanced technology process nodes up to 5nm FINFETs, executing: Floor Planning, Power Planning, Placement and optimization, Clock Tree Synthesis (CTS), Routing and optimization
- Physical Verification - Layouts are carefully checked with the industry standard tools, including parasitic extraction to confirm on spec operation before first silicon. Checks include DRC, LVS, ERC and customer specific checks
- Static Timing Analysis (STA) & closure - Post Layout Extraction Timing Analysis for multi modes & multi corners, Timing ECOs using TSO or manual for timing critical paths
- Power Analysis - EMIR analysis (static and dynamic): Power Integrity (Power EM and IR-Drop) and Signal Integrity (Sig EM, IR-Drop and Noise)